The production of quality semiconductor on insulator (SOI) structures for very large scale integration applications has become an important aspect of semiconductor fabrication particularly as the dimensions of transistors and other semiconductor structures become smaller and smaller. Semiconductor on insulator technology allows for this shrinkage in structure while providing greater isolation between devices. This isolation is necessary because the problems associated with electromagnetic interference and parasitic capacitance between the structures are magnified as the size of circuits is reduced.
Because silicon is the dominant semiconductor material in present day integrated circuit devices, much effort has been focused on improving silicon on insulator fabrication techniques. Of particular difficulty is controlling the etching of the silicon semiconductor substrate to stop at the thin silicon epitaxial layer. Various techniques have been employed in attempts to control substrate etching. For example, U.S. Pat. No. 3,997,381 to Wanless discloses forming a thin epitaxial silicon layer on a silicon substrate followed by forming a silicon oxide layer on the epitaxial layer. This layered device is bonded to an oxidized second substrate so that the epitaxial layer is sandwiched between the two substrates. The substrates are removed by etching to thereby expose the epitaxial layer. The electromotive force between an electrode pair immersed in the etchant solution is measured during etching, as an oxidizing agent is added, to thereby determine the proper etch end point. Another attempt to control etch end point is described in U.S. Pat. No. 4,601,779 to Abernathy et al in which a buried etch-stop layer is formed in an epitaxial layer by implanting oxygen or nitrogen ions therein. An oxide layer is grown on the epitaxial portion and is used to form a bond with the oxide layer of a support wafer. After bonding, the silicon substrate is etched until the etch-stop, to expose the epitaxial layer. The etch-stop is then removed to form a thin silicon layer having a uniform thickness.
There has also been an increased interest in forming nonsilicon semiconductor on insulator structures. Nonsilicon semiconductors, for example germanium (Ge), gallium arsenide (GaAs) and silicon germanium alloys (Si-Ge) are finding increasing uses in high temperature, high power, optoelectronic, radiation sensitive and other applications. Accordingly, the art has also focused on techniques for producing nonsilicon semiconductor on insulator structures. One such technique is disclosed in U.S. Pat. No. 4,226,649 to Davey et al in which an epitaxial layer of doped n-type gallium arsenide is formed on a germanium substrate. A semi-insulating N+layer of gallium arsenide is grown on the N-type active layer, and a thin cap of germanium is deposited on the composite. Gold is deposited onto the germanium cap to form an eutectic alloy layer with the germanium. The alloy is formed and the composite is bonded to a metal, glass or ceramic substrate. The germanium substrate is then removed to expose the N-layer of gallium arsenide for device formation.
While the Davey et al technique does provide a method of forming a gallium arsenide on insulator structure, the technique is complicated and expensive. A separate N+semiinsulating layer must be provided to prevent the gold layer from creating short circuits in the gallium arsenide. This N+layer may cause leakage problems, leading to degraded device performance and potential reliability problems. The gold bonding layer is expensive, and the large number of process steps creates an expensive gallium arsenide on insulator structure.